a. Field of the Invention
The invention relates to an organization for improving the efficiency of semiconductor random access memories and more particularly, to a semiconductor random access memory having a memory status indicator for indicating the availability of data.
B. Prior Art
Semiconductor integrated circuit random access memories (RAMs) have been known for several years. For example, an article entitled, "Integrated MOS Transistor Random Access Memory" by John D. Schmidt, in Solid State Design, January, 1965, pp. 21-25, describes a static RAM which may use a six transistor storage cell. See also U.S. Pat. No. 3,447,137.
It has been recognized in first in - first out shift registers (FIFO), that a "data shift flag" is advantageous for indicating the position of a data bit as it ripples through the register. For example, see U.S. Pat. No. 3,736,575. Although the "data shift flag" is not applicable to random access memories, it is a timing signal which is useful.
In the prior art, semiconductor memories were operated with times which were specified to be dependent on expected worst case conditions of semiconductor processing, temperature and voltage fluctuations. To meet acceptable specified performance levels, it was necessary to allow for the occasional occurrence of worst case conditions. Some very large systems control memory operation with signals which indicate memory status, but this is unknown in semiconductor memory.
It was our object to device a random access memory which operates at its fastest possible rate and not limited to worst case specifications.